1. Field of the Invention
The present invention relates to a switching power source apparatus for supplying a stable DC voltage.
2. Description of Related Art
A DC-DC converter for supplying a source voltage to a digital signal processing LSI such as an image engine or a CPU is required to have an improved load response to minimize variation in an output voltage when the LSI dynamically changes its load. To meet the requirement, some DC-DC converter employs an error amplifier to compare an output voltage with a reference voltage. The error amplifier, however, causes a delay that may deteriorate the load response of the DC-DC converter. To avoid the delay caused by the error amplifier, a device that is widely used is a ripple converter employing no error amplifier, and instead, adopting PFM (pulse frequency modulation) control to improve load response with respect to a load variation in the digital device.
A PFM ripple converter according to a related art detects a ripple voltage in an output voltage, and to obtain a sufficient ripple signal, employs as an output capacitor an electrolytic capacitor having a large ESR (equivalent series resistance). Due to the large ESR, the electrolytic capacitor hinders compactness of the ripple converter.
To deal with this problem, U.S. Pat. No. 6,583,610 (Patent Document 1) and Japanese Unexamined Patent Application Publication No. 2008-72891 (Patent Document 2) disclose a technique of superposing a ramp signal, which assumes a ripple to be produced by ESR, on a feedback voltage or reference voltage, to secure stable operation even when a ceramic capacitor having a small ESR is used as an output capacitor.
FIG. 1 is a circuit diagram illustrating a switching power source apparatus prepared according to the teachings of Patent Documents 1 and 2 and FIG. 2 is a timing chart illustrating operation of the apparatus of FIG. 1. With reference to FIGS. 1 and 2, operation of the switching power source apparatus employing the conventional ON-width-fixed ripple control technique will be explained. The technique disclosed in Patent Documents 1 and 2 superposes a ramp signal on a feedback signal. This technique is operationally equivalent to superposing a ramp signal on a reference voltage, and therefore, the apparatus and operation of FIGS. 1 and 2 will be explained in connection with superposing a ramp signal on a reference voltage because it is convenient when explaining embodiments of the present invention.
In FIG. 1, a ramp generator 18 generates a ramp signal Ramp, which assumes a ripple signal to be produced by ESR, and outputs the ramp signal Ramp to a superposing circuit 3. The superposing circuit 3 superposes the ramp signal Ramp on a first reference voltage REF, to generate a second reference voltage REF2 having a positive inclination and output the same to a positive input terminal of a feedback comparator 4.
A negative input terminal of the feedback comparator 4 receives a feedback voltage FB. The feedback voltage FB is produced by dividing an output voltage Vout by feedback voltage dividing resistors 16 and 17. If the feedback voltage FB is lower than the second reference voltage REF2, the feedback comparator 4 immediately outputs a signal FB_TRG to a one-shot circuit 5a. 
In response to the signal FB_TRG, the one-shot circuit 5a outputs a signal ON_TRG having a predetermined time width to a terminal Set of an ON timer 7b. 
A feedforward circuit 6b maintains a predetermined switching frequency even if an input voltage Vin and the output voltage Vout change. For this, the feedforward circuit 6b detects the input voltage Vin and output voltage Vout, generates a feedforward signal Iton that is proportional to the input voltage Vin and inversely proportional to the output voltage Vout, and outputs the feedforward signal Iton to a terminal Adj of the ON timer 7b. 
The ON timer 7b uses as a trigger the signal ON_TRG from the one-shot circuit 5a and outputs a signal Ton corresponding to the feedforward signal Iton to a drive logic 8. The larger the feedforward signal Iton, the narrower the time width of the signal Ton.
Based on the signal Ton from the ON timer 7b, the drive logic 8 outputs a drive signal Hon for a high-side driver 9 and a drive signal Lon for a low-side driver 10. The drive logic 8 detects, from a signal SW, that a regenerative period ends and the polarity of a current IL passing through an inductor 13 inverts, and then, changes the drive signal Lon from high to low to turn off a low-side MOSFET 12, thereby preventing the inductor current IL from excessively passing in a reverse manner and avoiding a useless loss.
In response to the signal Hon from the drive logic 8, the high-side driver 9 drives a gate of a high-side MOSFET 11, to supply energy through the inductor 13 to an output capacitor 14 and output load 15.
In response to the signal Lon from the drive logic 8, the low-side driver 10 drives a gate of the low-side MOSFET 12, to turn on the low-side MOSFET 12 in a regenerative period of the inductor current IL after the high-side MOSFET 11 is turned off, thereby reducing a conduction loss.
In this way, the switching power source apparatus of FIG. 1 turns on the high-side MOSFET 11 as soon as the output voltage Vout decreases due to a sudden change in an output load current Iout from light load to heavy load, thereby improving a load response.
In addition, the apparatus of FIG. 1 enables a ceramic capacitor of low ESR to be used as an output capacitor, which the related-art ripple control technique is unachievable.